submicron transistors and test structures fabricated using a mechanically planarized shallow trench isolation scheme which incorporates a poly-si trench field shield are discussed. the resulting devices have well-behaved transistors and excellent isolation characteristics on test structures with 0.6 mu m isolation. replacing field oxide areas with shallow dielectric filled trenches offers several potential advantages for deep submicron integrated circuit fabrication. the planar nature of this isolation scheme reduces the depth of field requirements for lithographic exposures, and therefore should facilitate the printing of submicron features. the lack of a bird's beak encroachment on active device areas will allow more efficient use of the si surface the presence of the field shield, connected to the tub si at the bottom of the trench, avoids leakages by preventing charges in the tetraethylorthosilicate (teos) filled trenches from reaching the trench sidewalls. for the same reasons, it is anticipated that this structure will exhibit favorable radiation immunity