multilevel interconnect schemes for integrated circuits generally require one or more planarization steps, in order to maintain an acceptably flat topography for lithography and thin-film step coverage on the higher levels. traditional approaches have involved planarization of the interlevel insulation (dielectric) layers, either by spin-on application (e.g., polyimide), or by reflow (e.g., phosphosilicate glass). we have pursued an alternative approach, in which each metal level is melted (hence planarized) using a pulsed laser prior to patterning. short (approx.1 mu s) pulses are used to preclude undesirable metallurgical reactions between the film, adhesion or barrier layer, and dielectric layer. laser planarization of metals is particularly well suited to multilevel systems which include ground or power planes. results are presented for planarization of gold films on sio sub 2 dielectric layers using a flashlamp-pumped dye laser. the pulse duration is approx.1 mu s, which allows the heat pulse to uniformly penetrate the gold while not penetrating substantially through the underlying sio sub 2 (hence not perturbing the lower levels of metal). excellent planarization of the gold films is achieved (less than 0.1 mu m surface roughness, even starting with extreme topographic variations), as well as improved conductivity. to demonstrate the process, numerous planarized two-layer structures (transmission lines under a ground plane) were fabricated and characterized. 9 refs., 2 figs. (era citation 11: 038653)